The invention is situated in the field of production of semiconductor devices, more particularly related to the removal of high dose and high energy implanted photoresist layers.
A photoresist layer is used as a mask during the high dose and high energy ion implantation step in the manufacturing process of semiconductors. During the implantation step, the upper surface of the photoresist layer is transformed to a carbonised crust which contains Arsenic, Phosphorus and/or Boron dopants. The thickness of the crust as well as the depth of the implanted species are directly related to the implantation energy and the type of dopant. Under the crust layer, the remainder of the photoresist layer is still present. The next step is removing the crust and unaffected photoresist layer selective to the underlying siliconoxide.
The technique of ion implantation using photoresist layers as mask material and the subsequent removal of this implanted photoresist are discussed in several documents, such as xe2x80x9cWafer Cooling and Photoresist Masking Problems in Ion Implantationxe2x80x9d by T. C. Smith, Motorola MOS group/Advanced Product RandD Labs, xe2x80x9cCarbonised Layer Formation in Ion Implanted Photoresistxe2x80x9d by K. J. Orvek and C. Huffman (Nucl. Instr. and Methods in Phys. Res., Vol B7/8(1985)p501), xe2x80x9cCharacterization of Ion-Implanted Photoresist Films by Fourier Transform Infrared Spectroscopyxe2x80x9d by J. Lee, C. Lee, J. Alvis and S. W. Sun, Motorola Advanced Products and Developments Laboratory, Austin, and in xe2x80x9cAshing of Ion-Implanted Resist Layerxe2x80x9d by S. Fujimura, J. Kono, K. Hikazutani and H. Yano (Japanese Journal of Applied Physics, Vol. 28, No. 10, October 1989, p. 2130), which are included by reference herein.
Standard dry strip processes are performed using a downstream oxygen plasma at high temperature (200-300xc2x0 C.) to increase the striprate. The energy transfer from the high energy ions to the photoresist during the implantation process leads to high stress in the photoresist. During high temperature treatment the crust will pop off due to differential stress in the carbonised, implanted and plain resist regions. This is enhanced by the volatile content trapped in the unaffected resist underneath the hardened crust. The use of oxygen in dry plasma stripping will enable oxidation of the implanted species. These phenomena give existence to redeposited resist flakes and oxidised dopants, which are difficult to remove.
The aim of the invention is to provide a new method for stripping the photoresist layer from a semiconductor device that has been treated with an ion implantation step, in which photoresist layer, crust layer and residues are completely removed with minimal oxide loss.
The invention concerns a method for stripping the photoresist layer and the crust from a semiconductor, that has preferably been treated with an ion implantation step, wherein the method comprises an ion assisted plasma step using a mixture of water vapour, helium and a F-containing compound in which radicals are generated, and the step of contacting said photoresist layer and crust with said radicals to remove said photoresist layer and crust from said semiconductor surface.
Preferably, said F-containing compound is CF4.
Preferably, said mixture is such that the screen oxide loss is less than half of the total oxide layer.
The ion implantation step is preferably a high dose and high energy ion implantation step. A high dose and high energy ion implantation step will give resist and crust layers that are hard to remove.
The ion assisted plasma step is preferably performed in an R.I.E. reactor. Preferably, the water vapour to helium ratio is comprised between 1:4 and 1:8.
The method according to the invention can further comprise a downstream oxygen plasma stripping step. Such step can be an O2-containing afterglow ashing step. The method can further comprise the step of a post wet cleaning step. Said post wet cleaning step is preferably performed with means comprising sulphuric acid and hydrogen peroxide and/or means comprising O3 and H2O and/or a DI water rinse.
Said ion assisted plasma step is preferably performed at a temperature between 15 and 140xc2x0 C., advantageously at a temperature of about 40xc2x0 C.
The RF power lies preferably between 200 and 1000 W, advantageously between 300 and 600 W.
The amount of water in the mixture lies preferably between 40 and 70 sccm.
In a preferred embodiment, the semiconductor, prior to the ion assisted plasma step using a mixture of water vapour, helium and CF4, is subjected to an ion assisted plasma step using a mixture of water vapour and helium.
A dilution of the mixture with He results in a low water vapour flow combined with a high total flow. The low water vapour flow is advantageous for residue removal, while the high total flow is important to minimise oxide loss.
The invention consists of using an optimised mixture of water vapour, helium and carbon tetrafluoride in the RIE plasma reactor, followed by a downstream oxygen plasma strip at high temperature.
Working at lower temperatures will eliminate resist popping, but the use of ionic bombardment is necessary to yield acceptable striprates. The resist layer is partially stripped in an RIE-type (Reactive Ion Etch) reactor using water vapour. This provides the hydrogen component which volatilises the implanted species in the crust layer by formation of As, B, or P hydrides. The remainder of the photoresist layer can then be removed in a downstream oxygen plasma process.
Ion implantation is performed through a screen oxide. This is a sacrificial oxide that is used to reduce channelling. The thickness of this screen oxide ranges from 15 to 40 nm. When scaling down devices, two implantation steps are performed subsequently to form source and drain regions, using the same screen oxide of typically 15 nm and two different photoresist masks. To be able to do this, oxide loss during stripping, especially for the first photoresist layer, must be minimised.
The use of water vapour has several disadvantages: it attacks silicon oxide and leaves residues along the structures. This is detailed below in the description of the figures.
Following the crust removal step as described higher, an O2 afterglow ashing step can be used to remove any remaining resist.
A separate wet chemical clean can be performed to achieve complete residue removal. This residue clean-up step can be done e.g. with a mixture of sulphuric acid and hydrogen peroxide, volume 8 liters, ratio 4:1, at 80xc2x0 C. during 10 minutes, followed by a rinse in deionized water. Another possibility is to use a cleaning procedure involving a moist O3 gas phase process (H2Oxe2x80x94O3 mixture) at 80xc2x0 C. for 10 min. A combination of several methods is also possible.
The invention will be disclosed by means of examples, which are to be regarded as non-limiting to the scope of the invention as disclosed in this document.
Preparation of Test Wafers
Oxidised silicon wafers were coated with 870 nm Sumitomo I-line resist, exposed to I-line radiation, developed and baked on a hotplate at 100xc2x0 C. These wafers were used in all examples for testing.
Implantation of phosphorus was performed through a 15 nm screen oxide, using a medium current ion implanter from Eaton. Implantation (I) and RIE strip (S) parameters are mentioned in table 1.
Silicon wafers as described before were implanted with parameters such as in Table 1. The implantation dose was 5.1015 atoms/cm2.
These wafers were exposed to a mixture of 67 sccm (Standard Cubic Centimeter: measurement at 760 mm Hg and 0xc2x0 C.) water vapour and 400 sccm helium during 40 seconds, followed by exposition to a mixture of 67 sccm water vapour, 400 sccm helium and 3 sccm CF4 during 20 seconds, both steps taking place in an RIE reactor (pressure at 650 millitorr, RF power at 500 W), resulting in removal of the crust without causing resist popping. The H2O: He ratio of the mixture is 1:6.
This is followed by a downstream oxygen plasma stripping step. This step removed all the residues originating from both resist layer and implanted species. Residues residing on structures smaller than 1 xcexcm were removed using a post wet cleaning step with a mixture of sulphuric acid and hydrogen peroxide (8 l, ratio 4:1) during 10 min at 80xc2x0 C.
The same process as in example 1 was used, except for the following differences:
implantation dose is 1.1016 atoms/cm2 
500 sccm helium in both steps
H2O:He ratio of 1:7.5
a pressure is 700 millitorr
6 sccm CF4 in second step.
The steps of downstream oxygen plasma stripping and wet cleaning result in a wafer that is free of residues.
Silicon wafers as described higher were used. After an ion implantation with a dose of 1.1016 atoms/cm2, the wafers are subjected to a pure water vapour plasma in an RIE reactor, resulting in the removal of the crust without any resist popping. Parameters for this step are:
60 seconds processtime,
150 sccm water vapour,
pressure at 400 millitorr, and
RF power at 450-500 Watt.
The steps of downstream oxygen plasma stripping and wet cleaning such as described higher result in a wafer that still has polymeric residues in the resist covered areas and especially at the edges of the resist layer pattern.
In this example, nearly the same process as described in example 3 is used, with the difference that the implantation dose is 5.1015 atoms/cm2 at 400 millitorr and 500 Watt, a first stripping step (with water vapour) was performed during 50 seconds and with 50 sccm water vapour, followed by a second strip using a mixture of 200 sccm water vapour and 2 sccm CF4 during 20 seconds.
Resist stripping was completed by downstream oxygen plasma stripping and wet cleaning, leaving residues long the pattern edge.
Oxide Loss and Residue Removal Results